FIFO design for IEEE 802.3 standard 10GBase-X PCS and XGXS sublayers

Thayaparan, S; Nanayakkara, A
URI: http://dl.lib.mrt.ac.lk/handle/123/10087

Abstract:

This paper analyses the FIFO design for the receiver of 10GBase-X PCS sublayers specified by IEEE 802.3 CSMA/CD Standards. The proposed FIFO design will save the gate count, power and the silicon area in ASIC design considerably.

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