Optimization of receiver FIFO for IEEE 802.3ba 40GBASE PCS sublayer

Abstract

Local Area Networks (LAN) are based on Ethernet technology. Commonly used 10 and 40 Gigabit Ethernet systems are adopting IEEE 802.3 standards. The aim of this dissertation is to optimize the FIFO design for the receiver of Physical Coding Sub layer (PCS) specified by IEEE 802.3 standards. This dissertation is having two phases. In the first phase, optimal FIFO for IEEE 802.3ae 10GBASE-X PCS receiver is designed and implemented. Proper operation of the proposed design is verified with simulation results. In the second phase, possible optimization for receiver FIFO of IEEE 802.3ba 40GBASE-R PCS layer is identified. Potential implementation for 40GBASE-R PCS is simulated with proposed FIFO design, to verify the proper functionality. Proposed designs will save gate count, power and the silicon area of ASIC design considerably. As future work it is suggested to emulate the proposed design with a suitable hardware.