Show simple item record

dc.contributor.author Wijesinghe, T
dc.contributor.author Senevirathne, K
dc.contributor.author Siriwardhana, C
dc.contributor.author Visitha, W
dc.contributor.author Jayasena, S
dc.contributor.author Rusira, T
dc.contributor.author Hall, M
dc.date.accessioned 2018-08-03T21:26:16Z
dc.date.available 2018-08-03T21:26:16Z
dc.date.issued 2017
dc.identifier.uri http://dl.lib.mrt.ac.lk/handle/123/13359
dc.description.abstract Abstract—Loop tiling is a useful technique used to achieve cache optimization in scientific computations. However, general loop tiling techniques usually fail to improve parallelism in certain scientific computations due to dependences among execution steps. In this paper we implement and experiment on a tiling technique known as Parameterized Diamond Tiling designed based on the data dependences in the program. We implement this tiling scheme in the CHiLL compiler and demonstrate its performance for 4 stencil computations of which, outputs are calculated as a function of neighbouring points. As one of the primary goals of parameterization, in this paper we observe the impact of tile sizes on performance. en_US
dc.title Parameterized diamond tiling for parallelizing stencil computations en_US
dc.type Conference-Abstract en_US
dc.identifier.faculty Architecture en_US
dc.identifier.department Department of Computer Science and Engineering en_US
dc.identifier.year 2017 en_US
dc.identifier.conference Moratuwa Engineering Research Conference - MERCon 2017 en_US
dc.identifier.place Moratuwa, Sri Lanka en_US
dc.identifier.email theekshana.12@cse.mrt.ac.lk en_US
dc.identifier.email kithmini.12@cse.mrt.ac.lk en_US
dc.identifier.email chathuras.12@cse.mrt.ac.lk en_US
dc.identifier.email visitha.12@cse.mrt.ac.lk en_US
dc.identifier.email sanath@cse.mrt.ac.lk en_US


Files in this item

This item appears in the following Collection(s)

Show simple item record