Abstract:
Multi field packet classification is the enabling function for many novel and emerging network applications. Exponential growth of Internet traffic and classification rule
sets demand novel hardware based architectural approaches to packet classification. Even though this is an immensely studied area, packet classification that supports scalability in both line rates and rule sets is scarce. In this paper we present experience
gained while implementing a parallel packet classification engine architecture on a popular reconfigurable router platform. The architecture exploits parallelism offered in modern hardware technologies to classify multiple packets simultaneously to increase the throughput. The architecture is also capable of utilizing temporal locality present in internet traffic to increase the throughput. The Architecture was implemented on NetFPGA
platform and packet classification was done at full line rate without degrading the data rate or the round trip time.
