dc.contributor.author |
Pulipati, S |
|
dc.contributor.author |
Ariyarathna, V |
|
dc.contributor.author |
Dhananjay, A |
|
dc.contributor.author |
Eltayeb, ME |
|
dc.contributor.author |
Mezzavilla, M |
|
dc.contributor.author |
Jornet, JM |
|
dc.contributor.author |
Mandal, S |
|
dc.contributor.author |
Bhardwaj, S |
|
dc.contributor.author |
Madanayake, A |
|
dc.contributor.editor |
Weeraddana, C |
|
dc.contributor.editor |
Edussooriya, CUS |
|
dc.contributor.editor |
Abeysooriya, RP |
|
dc.date.accessioned |
2022-08-09T09:56:45Z |
|
dc.date.available |
2022-08-09T09:56:45Z |
|
dc.date.issued |
2020-07 |
|
dc.identifier.citation |
S. Pulipati et al., "Xilinx RF-SoC-based Digital Multi-Beam Array Processors for 28/60 GHz Wireless Testbeds," 2020 Moratuwa Engineering Research Conference (MERCon), 2020, pp. 254-259, doi: 10.1109/MERCon50084.2020.9185240. |
en_US |
dc.identifier.uri |
http://dl.lib.uom.lk/handle/123/18584 |
|
dc.description.abstract |
Emerging wireless applications such as 5G cellular,
large intelligent surfaces (LIS), and holographic massive MIMO
require antenna array processing at mm-wave frequencies with
large numbers of independent digital transceivers. This paper
summarizes the authors’ recent progress on the design and testing
of 28 GHz and 60 GHz fully-digital array processing platforms
based on wideband reconfigurable FPGA-based software-defined
radios (SDRs). The digital baseband and microwave interfacing
aspects of the SDRs are implemented on single-chip RF systemon-
chip (RF-SoC) processors from Xilinx. Two versions of the
RF-SoC technology (ZCU-111 and ZCU-1275) were used to
implement fully-digital real-time array processors at 28 GHz
(realizing 4 parallel beams with 0.8 GHz bandwidth per beam)
and 60 GHz (realizing 4 parallel beams with 1.8 GHz bandwidth
per beam). Dielectric lenslet arrays fed by a digital phased-array
feed (PAF) located on the focal plane are proposed for further
increasing antenna array gain. |
en_US |
dc.language.iso |
en |
en_US |
dc.publisher |
IEEE |
en_US |
dc.relation.uri |
https://ieeexplore.ieee.org/document/9185240 |
en_US |
dc.subject |
Wireless |
en_US |
dc.subject |
5G |
en_US |
dc.subject |
beamforming |
en_US |
dc.subject |
FPGA |
en_US |
dc.subject |
RF-SoC |
en_US |
dc.title |
Xilinx rf-soc-based digital multi-beam array processors for 28/60 ghz wireless testbeds |
en_US |
dc.type |
Conference-Full-text |
en_US |
dc.identifier.faculty |
Engineering |
en_US |
dc.identifier.department |
Engineering Research Unit, University of Moratuwa |
en_US |
dc.identifier.year |
2020 |
en_US |
dc.identifier.conference |
Moratuwa Engineering Research Conference 2020 |
en_US |
dc.identifier.place |
Moratuwa, Sri Lanka |
en_US |
dc.identifier.pgnos |
pp. 254-259 |
en_US |
dc.identifier.proceeding |
Proceedings of Moratuwa Engineering Research Conference 2020 |
en_US |
dc.identifier.email |
amadanay@fiu.edu |
en_US |
dc.identifier.email |
j.jornet@northeastern.edu |
en_US |
dc.identifier.email |
aditya@courant.nyu.edu |
en_US |
dc.identifier.email |
mohammed.eltayeb@csus.edu |
en_US |
dc.identifier.email |
soumyajit@ece.ufl.edu |
en_US |
dc.identifier.doi |
10.1109/MERCon50084.2020.9185240 |
en_US |