Abstract:
From the early Fanes of foreign trade which consisted of direct exchange of commodities, financial exchanges have evolved to process transactions using high end computer systems. In highly competitive financial markets low latency and high throughput have become the utmost concern for all solution providers for financial exchanges The Financial Information eXchange (FIX) Protocol is one of the most commonly used protocols in financial trading systems The processing of this protocol is current/} being done on software and the advancements have been such that data processing on software has reached its saturation and solution providers for stock exchanges are nowadays researching for possibilities of improving the latency and throughput. The high level of parallelism in hardware implementations compared to software has made hardware the only possible solution for this increasingly high demand Thus, our solution is an implementation of the FIX protocol on Field Programmable Gate Array (FPGA) s which offloads the processing of the FIX protocol to a FPG. I Board interfaced through PC I Express. This processing core successfully implemented on a Xilinx Virtex 5 FPGA, consists of a Decoder and an Encoder for version 4.2 of the FIX protocol. It processes 5 million messages per second for encoding and 3.8 million messages per second for decoding and has latencies of only 170-330 nanoseconds for encoding and 180-360 nanoseconds for decoding where as the best figures obtained so far in the software approach is a throughput of20,000 messages per second and a latency of 50 microseconds.
