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dc.contributor.author Gamage, S
dc.contributor.author Pasqual, AA
dc.date.accessioned 2018-12-18T20:40:04Z
dc.date.available 2018-12-18T20:40:04Z
dc.identifier.uri http://dl.lib.mrt.ac.lk/handle/123/13738
dc.description.abstract Multi field packet classification is the enabling function for many novel and emerging network applications. Exponential growth of Internet traffic and classification rule sets demand novel hardware based architectural approaches to packet classification. Even though this is an immensely studied area, packet classification that supports scalability in both line rates and rule sets is scarce. In this paper we present experience gained while implementing a parallel packet classification engine architecture on a popular reconfigurable router platform. The architecture exploits parallelism offered in modern hardware technologies to classify multiple packets simultaneously to increase the throughput. The architecture is also capable of utilizing temporal locality present in internet traffic to increase the throughput. The Architecture was implemented on NetFPGA platform and packet classification was done at full line rate without degrading the data rate or the round trip time. en_US
dc.language.iso en en_US
dc.subject Internet, NetFPGA, Packet classification, Reconfigurable Systems, Rule Caching en_US
dc.title Line rate parallel packet classification module for NetFPGA platform en_US
dc.type Conference-Abstract en_US
dc.identifier.faculty Engineering en_US
dc.identifier.department Department of Electronic and Telecommunication Engineering en_US
dc.identifier.year 2013 en_US
dc.identifier.conference IEEE 8th International Conference on Industrial and Information Systems - 2013 en_US
dc.identifier.place Peradeniya, Sri Lanka en_US
dc.identifier.pgnos pp. 277 - 282 en_US
dc.identifier.email fsamoda@ent.mrt.ac.lk en_US
dc.identifier.email pasqualg@ent.mrt.ac.lk en_US
dc.identifier.doi 10.1109/ICIInfS.2013.6731995 en_US


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