Hardware assisted IP stack
dc.contributor.author | Ellawala, NM | |
dc.contributor.author | Kehelwala, KGDC | |
dc.contributor.author | Koggalahewa, NA | |
dc.contributor.author | Kotagodahetti, RPK | |
dc.contributor.author | Pasqual, AA | |
dc.date.accessioned | 2013-10-21T02:12:25Z | |
dc.date.available | 2013-10-21T02:12:25Z | |
dc.date.issued | 2011 | |
dc.description.abstract | TCP/IP performance improvement is a major concern in low latency network applications. The network interface speed is a significant factor to be concerned on, when working with applications that require high speeds such as datacenter applications in cloud computing environments. This paper presents on the processing speed improvement of the IP layer of the TCP/IP stack. This will he mainly realized through hardware implementation of the IP layer functions. The system is implemented on a FPGA based hardware platform. Our Main objective is to study about the achie\>able performance gains by implementing a scalable hardware based IP layer. | |
dc.identifier.conference | Excellence in Research, Excelling a Nation | |
dc.identifier.pgnos | 132-134 | |
dc.identifier.place | Faculty of Engineering, University of Moratuwa | |
dc.identifier.proceeding | 17th Annual Research Symposium on Excellence in Research, Excelling a Nation | |
dc.identifier.uri | http://dl.lib.mrt.ac.lk/handle/123/8086 | |
dc.identifier.year | 2011 | |
dc.language | en | |
dc.title | Hardware assisted IP stack | |
dc.type | Conference-Abstract |
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