Parameterized diamond tiling for parallelizing stencil computations

dc.contributor.authorWijesinghe, T
dc.contributor.authorSenevirathne, K
dc.contributor.authorSiriwardhana, C
dc.contributor.authorVisitha, W
dc.contributor.authorJayasena, S
dc.contributor.authorRusira, T
dc.contributor.authorHall, M
dc.date.accessioned2018-08-03T21:26:16Z
dc.date.available2018-08-03T21:26:16Z
dc.date.issued2017
dc.description.abstractAbstract—Loop tiling is a useful technique used to achieve cache optimization in scientific computations. However, general loop tiling techniques usually fail to improve parallelism in certain scientific computations due to dependences among execution steps. In this paper we implement and experiment on a tiling technique known as Parameterized Diamond Tiling designed based on the data dependences in the program. We implement this tiling scheme in the CHiLL compiler and demonstrate its performance for 4 stencil computations of which, outputs are calculated as a function of neighbouring points. As one of the primary goals of parameterization, in this paper we observe the impact of tile sizes on performance.en_US
dc.identifier.conferenceMoratuwa Engineering Research Conference - MERCon 2017en_US
dc.identifier.departmentDepartment of Computer Science and Engineeringen_US
dc.identifier.emailtheekshana.12@cse.mrt.ac.lken_US
dc.identifier.emailkithmini.12@cse.mrt.ac.lken_US
dc.identifier.emailchathuras.12@cse.mrt.ac.lken_US
dc.identifier.emailvisitha.12@cse.mrt.ac.lken_US
dc.identifier.emailsanath@cse.mrt.ac.lken_US
dc.identifier.facultyArchitectureen_US
dc.identifier.placeMoratuwa, Sri Lankaen_US
dc.identifier.urihttp://dl.lib.mrt.ac.lk/handle/123/13359
dc.identifier.year2017en_US
dc.titleParameterized diamond tiling for parallelizing stencil computationsen_US
dc.typeConference-Abstracten_US

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