Reconfigurable hardware design of NTT-based polynomial multiplication accelerator for post quantum cryptography

Abstract

The rise of quantum computing threatens existing encryption schemes, prompting NIST to standardize Post-Quantum Cryptography (PQC) algorithms. In August 2024, NIST standardized a quantum-resistant Key Encapsulation Mechanism (KEM) based on the CRYSTALS-Kyber algorithm as a Federal Information Processing Standards (FIPS). Kyber relies on lattice-based cryptography, specifically the Module Learning with Errors (MLWE) problem, requiring computationally expensive modular polynomial multiplications. Efficient techniques like Number Theoretic Transform (NTT) and Pointwise Multiplication (PWM) optimize these calculations. Hardware accelerators are essential to perform these calculations efficiently. Butterfly units are the core components of such hardware accelerators, incorporating modular arithmetic operators. This work presents optimized modular operators utilizing digital signal processing (DSP) units, reducing the A × T ratio and power consumption. Additionally, a manually designed reconfigurable butterfly unit is proposed, enhancing polynomial multiplication efficiency with lower power usage and improved performance over existing implementations.