FIFO design for IEEE 802.3 standard 10GBase-X PCS and XGXS sublayers
| dc.contributor.author | Thayaparan, S | |
| dc.contributor.author | Nanayakkara, A | |
| dc.date.accessioned | 2014-06-25T12:46:50Z | |
| dc.date.available | 2014-06-25T12:46:50Z | |
| dc.date.issued | 2014-06-25 | |
| dc.description.abstract | This paper analyses the FIFO design for the receiver of 10GBase-X PCS sublayers specified by IEEE 802.3 CSMA/CD Standards. The proposed FIFO design will save the gate count, power and the silicon area in ASIC design considerably. | en_US |
| dc.identifier.conference | International Conference on Intelligent Systems, Modelling and Simulation [4th] - ISMS | en_US |
| dc.identifier.department | Department of Electronic and Telecommunication Engineering, | en_US |
| dc.identifier.email | thayaparan@ent.mrt.ac.lk | en_US |
| dc.identifier.faculty | Engineering | en_US |
| dc.identifier.pgnos | pp. 589-591 | en_US |
| dc.identifier.place | Bangkok | en_US |
| dc.identifier.uri | http://dl.lib.mrt.ac.lk/handle/123/10087 | |
| dc.identifier.year | 2013 | en_US |
| dc.language.iso | en | en_US |
| dc.source.uri | http://www.ieee.org/conferences_events/conferences/conferencedetails/index.html?Conf_ID=30904 | en_US |
| dc.title | FIFO design for IEEE 802.3 standard 10GBase-X PCS and XGXS sublayers | en_US |
| dc.type | Conference-Abstract | en_US |